Optimized Signal Integrity
A bag of tricks to make the board work
by Rick Miller
R Miller & Associates, Inc.
1. Introduction: Why Signal Integrity?
4. Selecting Series Termination Resistors.
5. Tuning Series Termination Resistors
1. Introduction: Why Signal Integrity?
It is surprising how many electrical engineers will design modern high-speed digital circuit boards without handling the transmission line issues. The same engineers would not release an analog design board to production without first scoping out the intermediate analog signals. At high speed, all boards are analog, and it takes careful engineering to make them digital instead.
If your PCB fails at low temperature for unknown reasons, this may help. As silicon gets colder, the internal resistance drops, and output transitions become faster. Signal crosstalk and ringing will be worse at low temperature and high voltage. For a worst case test, increase the operating voltage to the upper tolerance limit, and cool the product to the minimum operating temperature.
 |
 |
Ringing high |
Ringing low |
Figure 1.1 Fast edges will do this at the receiver end, even on short PCB traces. The receiver chip will see double the power supply for rising signals, and negative supply voltage on falling inputs. The chip will not be happy with this.
If one unit works at worst case, this does not mean there are no signal integrity problems with the design. Sometimes the problems are not noticed until many units have been built and field returns begin. The engineering work is not done until every interconnect has been examined with an oscilloscope and tweaked. Fortunately the signal integrity problems are very obvious at room temperature with a good oscilloscope, but careful design starts with the circuit board.
2. PCB Stackup
As logic has become faster and faster, the circuit board itself has become the key component of high speed digital design. In the past, one could just route traces any way that was convenient, minimize the PCB layers to save money, and it would all work fine. Not so anymore. Spending some more money on terminations and extra board layers has become a wise investment. Much cheaper than customer returns and missed ship dates.
How many layers should your board have? Usually the answer is as few as possible, but minimizing the layers could be a disaster for the product. When using CMOS high speed digital devices, it will be necessary to locate series termination resistors as close as possible to the driving pins, and far away from the receiver pins. This puts most of the action on the surface layers, and will require a ground return current directly underneath them to contain the emissions and provide good clean signals. If the ground plane is missing, the current will return via the lowest available impedance. The impedance of free space is 377 Ω. The impedance of nearby traces is probably less than 377 Ω, so nearby traces will show this as crosstalk.
.
Figure 1.1 This is crosstalk during an SDRAM burst read from an MPC5200B. This board has no ground plane, so the signals splatter everywhere. Adding ground planes to the PCB will save a lot of radiated EMI and reliability problems. Scale: 0.5V /div and 20 nS /div.
A board with components on both sides will then need four layers just to handle the surface connections. Add another for power distribution and another for clock distribution plus signal routing. Here is a minimal six layer stackup:
| Layer |
Layer Use |
Notes |
| 1 |
Components, with series termination resistors |
Width of trace and distance to ground plane establishes board impedance. |
| 2 |
Ground Plane |
|
| 3 |
Clock distribution and signal routing |
Embedded microstrip. Match impedance to surface layers to avoid reflections. |
| 4 |
Power Plane |
|
| 5 |
Ground Plane |
|
| 6 |
Components, with series termination resistors |
Width of trace and distance to ground plane establishes board impedance. |
Table 2.1: Absolute minimum layer stackup for an MPC5200B design. More layers are probably needed to fit a dense board. See reference 1 and 6 for best practices.
Best practice for clock distribution is on an internal layer bounded by ground planes on each side. This effectively places the clock in a coaxial cable, called an embedded microstrip. Such an arrangement will minimize radiated emissions, which also minimizes induced crosstalk onto other traces. See reference 1 and 6 for some very detailed multilayer PCB best practices.
3. PCB Traces
Gone are the days when one could just run traces haphazardly. Some extremely high speed devices, like serializer/deserializer chips require matched length traces that run parallel to each other with minimum right angle turns.
Series termination resistors are not required if the traces are short and the risetimes are long. So what makes a short trace or a long risetime? Figure 5.2 shows a typical MPC5200B SDRAM controller output pin ( see reference 4 ) with a fall time of about 500pS. Effectively this is a 1 GHz signal, since half a cycle takes 500 pS. A typical FR4 PCB has a propagation delay of about 150 – 200 pS per inch, depending on whether the trace is on the surface or internal. In 500pS on this typical PCB, the half cycle wavelength will therefore measure about 3 inches. A 3 inch unterminated trace would therefore be a 1 GHz resonant circuit, with huge reflections back and forth. Assuming that the reflections last for about 7 cycles, we have about 7 nS before the signal stabilizes. How much shorter should it be to avoid a termination requirement? The general rule of thumb is about 1/6 of this length to qualify as a lumped circuit, with minimal transmission line effects. So this means a PCB trace longer than ½ inch will act as a transmission line for 500 pS edges.
.
Figure 3.1 Comparison of fall times versus PCB length occupied during that fall time.
That was a fast SDRAM output line, but the MPC5200B also has general purpose I/O that operates much slower. A 2 nS risetime would see 2 inches or more as a transmission line. Perhaps there is an enable line for a slow device on the PCB 4 inches away. Do we need a series termination resistor for it? Yes, because the device has a high input impedance compared to the board impedance, and will reflect the entire signal back. The resulting input will be double the power supply voltage input for rising edges, and –Vdd for falling edges. The slow device might withstand this for a time, but it is likely out of spec, and can contribute to more crosstalk and reliability concerns.
Pick a trace width and stay with it. Make sure a given trace does not vary in width, as this will vary the line impedance and make it very difficult to tune for optimized signal integrity. Variations in trace width are especially troublesome on bidirectional data lines. Ideally bidirectional lines have a resistor at each extreme end to control reflections, but often these traces are so short that only one resistor will fit in the available space. If the trace width on one side of this resistor is different than the trace width on the other side, then the line impedance will differ on both sides. This forces the engineer to tune the resistor to some compromise value, at best. A read operation will require different tuning than a write operation.
To minimize crosstalk between traces, it is suggested to use a spacing of two trace widths. If the trace width is 6 mils, then we need 12 mils between the outer edges to minimize crosstalk. This means the centerline of the traces will be 18 mils apart. This will insure the trace couples to the nearby ground plane, instead of the next trace. This is especially important for clock lines. Note that this works only with a ground plane directly underneath, because the ground plane presents a low impedance path to the nearby traces. If the ground plane is missing, the current will return via the lowest available impedance. The impedance of free space is 377 Ω. The impedance of nearby traces is probably less than 377 Ω, so nearby traces will show this as crosstalk.
4. Selecting Series Termination Resistors
For CMOS, using series termination resistors is the best practice. They yield excellent results, but must be tuned to work well. The first step of tuning is to pick a close value to start with. This is done by calculating the impedance of the PCB, and matching it exactly with the resistor + driver output resistance. When using a Freescale MPC5200B for example, the IBIS model for output impedance is well under one Ohm, and can be ignored. So the series termination resistor should be set to the designed PCB impedance. Here is a link about series termination resistor accuracy.
Using series termination is a kind of trick. We know that a CMOS output is very low impedance, but the input is very high impedance. So sending a signal along this transmission line is destined to produce a complete reflection (3). The trick is to send only half of the signal out, and the reflection will fill it out perfectly. See Figure 4.1.
.
Figure 4.1 Voltage divider trick with series termination resistors. Since a full reflection is expected, just send half the signal, and let the reflection fill it out.
The PCB stackup and trace width must be known before selecting the series termination resistors. To some extent the PCB impedance can be specified, but the real world often dictates otherwise. The final product will probably have some PCB thickness constraints, and the component pitch and layout will dictate the maximum trace width. The critical measurements are the trace width, and distance from the trace to the ground plane. These two primarily determine the PCB impedance. The exact formula for impedance is very complicated, and even the web based calculators are just approximations. Use reference 2 or similar to calculate your PCB impedance.
.
Figure 4.2 Databus series termination resistor placement. Note that the small values used for R_write and R_read do not affect the reflections. They are small compared to a CMOS input resistance. Imagine Figure 4.1 operating in both directions.
This PCB characteristic impedance is what the series termination resistors will be close to. Subtract the drive output impedance for a few first pass prototypes. Be aware that the driver output resistance for high and low outputs are not equal. Also the devices at each end will have differing resistances as well. A compromise will be needed at each end.
5. Tuning Series Termination Resistors
Tuning the first prototypes requires some test software that can exercise the lines in a controlled manner. For bidirectional data lines one must tune the read and write operations separately. This is because the probe must be connected to the receiving end of each transmission. The series termination resistor is designed to yield the best receive signal. The output driver will receive a nasty reflection from the series termination resistor. Start first with the single ended lines, such as address and control signals. They are much easier.
.
 |
 |
R/W databus |
Probe placement |
Figure 5.1 Left: Read/Write databus waveform. Note that the top trace shows ringing on the first pulse, but not the second. The bottom trace is the opposite. This is because the first pulse is a read from DRAM, while the second pulse is a write from the MPC5200B to DRAM. The top trace is probed at the DRAM, while the bottom trace probed at the 5200B. Right: Diagram of R/W probe placement on the data bus. All tuning measurements are taken at the receiver pins. Always probe at the receive end of the transmission line.
To begin, solder a very low capacitance probe socket or connector directly to the receiver chip pin. Keep the tip and ground connections as short as possible to get accurate readings, and to minimize skewing the impedance. If unsure about the probe, add a second identical probe to the first and see what changes happen. If very little changes, you have an excellent probe. Otherwise, one may need to mentally subtract the effect of the probes from the scope trace. Swap the two probes to make sure they are identical. Another test is to move the probe coax around and see if the waveform changes. It usually does with plain 10:1 probes.
Once the probe effect is known, observe the signal at the receiver and mentally subtract the probe effect. We are looking to change the resistor until the signal looks digital with a minimum of analog effects. If the signal has a slow risetime with no overshoot at all, and large undershoot, the resistor is probably too big and may skew your timing. Overshoot is when the voltage is headed towards either high or low, and goes past the target, overshooting it. Undershoot is when the target voltage is approached, but not quite reached.
|
 |
Complete reflection |
Resistor a bit low |
Figure 5.2 Left shows complete reflection without any resistor, and about 3 V overshoot. Right shows about 0.25V overshoot: increase the resistor 10-20% and retest. Both are about 1V/division.
 |
 |
Resistor too big. |
Tuned clock line. |
Figure 5.3 Left shows too much undershoot, decrease the resistor. Right shows some small undershoot which may be due to probe loading. A little bit of undershoot will provide a safety margin if faster parts, higher voltage, or colder temperatures occur. Both are about 1V/division.
If the signal rings wildly, then increase the resistor value in steps until it looks clean with a good risetime.
If the selected resistor yields about 100mV of undershoot, you are done with this line. A little bit of undershoot is a safety margin if faster parts, higher voltage, or colder temperatures occur. Typical digital logic is specified for at most 300mV of overshoot over the temperature range. Some chips can tolerate as much as 2V of overshoot for a few nanoseconds, but there is still a problem with this. Adjacent crosstalk will be proportional to the risetime and signal amplitude, so tune it anyway to minimize interference. The left waveform from Figure 5.2 will cause twice the crosstalk as the right waveform. Another problem is second sourcing the part. If the second source or replacement cannot handle the 2V overshoot, there will be problems.
A ringing line will also radiate a lot of energy that will interest the FCC. One way to see this is to use a spectrum analyzer to snoop the signal. Wrap about 10 turns of wirewrap wire around a 2cm rod in a flat plane to make a near-field antenna. Glue or tape it flat. A book highlighter makes a good form for this. Solder the antenna to a short coax and feed it to the spectrum analyzer. Set the analyzer to sweep the range of 30 MHz to 2 GHz and move the coil around the path of the overshooting signal. There will probably be a pattern of fundamental and overtone spikes seen. A well tuned line will drop these radiations by 40 dB. Multiply this by 200 or more board traces to understand the full effect. A well tuned board can pass FCC emissions without spending money on a shield.
6. Controlling Drive Strength
Many programmable logic devices have drive strength options. If the series termination resistors are properly tuned, and the PCB is well designed, then drive strength is not an issue. But if the real world has dumped a mess on your desk, then reducing drive strength can help. Reducing the drive strength has the effect of slowing the rise and fall times, which effectively decreases the transmission line effects.
 |
 |
Clock, high drive |
Clock, low drive |
Figure 6.1 No series termination resistors, with high drive strength on the left, and low drive on the right, about 1V/division. Ground is indicated by the triangle at left. Both signals are strongly loaded with a capacitor - not a good practice. Note how the rise and fall times are longer at low strength. Both are still way out of spec for most devices, but the low drive strength has a better chance of working.
7. Get the Board Working
Sometimes we inherit an incomplete design and have to make it work. Someone forgot to put series resistors on every high speed line, or put them at the receiver chip end, bad (slotted) or missing ground plane, etc. Here are a few tricks to get the prototypes running. Some of these are temporary fixes, not suitable for production, but will buy some time while the board is improved.
· First of all, do not put capacitors on the lines to tame the ringing. All this does is change the frequency of the ringing, and maybe increase the amplitude as well. Instead we need to dissipate the ringing energy as heat.
· If signal traces are routed across a slotted ground plane, this will force a voltage difference across that slot. One can tack several small bypass capacitors across the gap to clean up the resulting reflections. Use some 100 pF mixed with 0.1 uF for wide frequency coverage.
· Add resistors. Traces can be cut, and small series resistors can be tacked in-line to clean up the design. Put them as close to the driver chip as possible and tune for best receiver signal as usual. If this is a bidirectional line, try resistors at each end if possible. As a compromise put the resistor in the middle.
· Add AC terminators. This method adds a series RC in parallel with the receiver end to show a low AC impedance to the signal. Typical values are in the range of 33 Ohms and 22 pF, but depend greatly on PCB impedance and signal risetimes. Connect the capacitor directly to the line, and the resistor to the ground, with a common node. This arrangement permits measuring the current flowing through the resistor with a voltage probe. This current can easily reach 50-100 mA for a few nanoseconds. Make sure you read reference 5 before using an AC terminator.
Figure 7.1 Left: AC terminator, Right Schottky diodes
· Add Schottky diode clamps. Use fast, low voltage, low capacitance Schottky diodes at the receiver end to conduct the ringing energy back to the power and ground planes. Try type BAT54S as a starting point. Such diodes have a low forward drop of 200mV at low current. Typical peak currents of 50mA will raise this clamp voltage considerably above 700mV, which will violate most IC specs, but will at least get the prototype going at room temperature. Another problem is the turn-on delay of about 1nS, so the diode will not get all the ringing. This is a band-aid at best, used when other methods are not available or effective.
 |
 |
Clock, high drive + Schottky diodes. |
Clock, low drive + Schottky diodes. |
Figure 7.2 This is a copy of Figure 6.1 after adding BAT54 Schottky diodes to the SDRAM receiver chip, at it’s pins. Left is high drive strength, right is low drive strength. This low drive strength plus the diodes allowed the prototype to function, but it still violates most IC specs, because it reaches -0.8V. Scale is about 1V/div.
8. Q & A
Q: My clock frequency is only 50 MHz, so why worry about transmission line effects?
A: The real problem is the signal transition time, not the frequency of transitions. If your 50 MHz clock is generated by modern high-speed logic, it might as well be 500 MHz to the PCB. It needs to be an embedded stripline to keep it clean, and prevent crosstalk everywhere else.
Q: My last board design didn’t need terminators, so why should my new design?
A: Perhaps the earlier design needed terminators too. Were there some defective boards that had no other explanation? Look at the signals with a fast oscilloscope and you may be surprised. Also, newer chips are faster than the older ones, so transmission line effects will be more pronounced using newer parts.
Q: Why put the series termination resistor at the driver pin? Can’t I just put it anywhere on the trace?
A: Referring to Figure 4.1, the idea is to send only half the signal down the trace, because we know it will double when it bounces. We can take advantage of this doubling by sending only half the signal at first. Suppose the resistor was placed at the receiver pin instead, and we are using 3.3V logic on a 50 Ω board. This means that the full signal of 3.3V will travel down the 50 Ω trace and suddenly hit your 50 Ω resistor touching a 10kΩ or so CMOS input. The 50 Ω resistor will factor into the reflection according to the equation of reference 3 as follows:
Reflection ratio = ( 10,050Ω - 50Ω ) / ( 10,050Ω + 50Ω ) = 0.99
This is nearly a complete reflection, so expect a 6.6V signal at your CMOS input. The result would be the same if no resistor were used. If you put the resistor in the middle instead it will provide some benefit, but there will be extra reflections back and forth between the output pin and the resistor. This is a good compromise for a databus if there is not enough room to put two resistors per data line as in Figure 4.2.
Q: I changed the series termination resistors up and down, but still get ringing. How can I fix this?
A: Figure 7.3 is an example of such a situation on an SDRAM clock pin. This PCB has no ground plane, so this is a mess to start with. Note how changing the resistor only moved the ringing up or down. An AC terminator of 8.2pF and 10 Ω did not help, as shown in Figure 7.4. The ringing time constant is too close to the transition time constant to separate them. The solution was to tack a BAT54S Schottky diode at the SDRAM receiver pin, then adjust the resistor for best signal as in Figure 7.5.
Figure 7.3: SDRAM clock pin. Note how changing the resistor only moved the ringing up or down. Middle ringing can cause overclocking, and used 120 Ω here. Next trace up is 68 Ω but causes overshoot. Top trace is 47 Ω, with serious overshoot, but it prevents overclocking. Scale is 1V/div and 2.5nS/div. The ringing is close to 1 GHz.
Figure 7.4: This was a failed attempt to fix it with an AC terminator. An AC terminator of 8.2pF and 10 Ω was soldered to the RAM clock pin. The dark trace has a 0 Ω series termination resistor, which prevents the overclocking, but causes over 1V overshoot. The green trace uses 33 Ω to tame the overshoot, but this clock line has mid-voltage transitions that can cause overclocking. The ringing time constant is too close to the transition time constant to separate them. Both waveforms are unacceptable.
Figure 7.5: Green trace is the original signal using 120 Ω on this SDRAM clock line. Dark trace uses a Schottky diode soldered near the SDRAM clock pin to ground, and a 47 Ω series termination resistor. Another Schottky diode should be added between the pin and Vdd to remove the overshoot of Vdd. Note how the ground overshoot and overclocking have been eliminated. Scale is 1V/div and 2.5nS/div. The ringing is close to 1 GHz.
References
1 . "High-Speed Digital Design, A Handbook of Black Magic" by Johnson & Graham. Simply the best book out there on these topics. If this article was at all helpful, read it. The author also has a collection of topics at http://www.sigcon.com/pubsAlpha.htm
2. PCB impedance calculations: www.emclab.umr.edu/pcbtlc/ If this link breaks, you can search for another one.
3. The reflections are given by ( R-Z ) / ( R + Z ), where Z = the PCB impedance, and R = the chosen resistor + driver resistance. If no resistor is chosen, then expect a full reflection. Good luck.
4. Information about the Freescale MPC5200B is at: www.freescale.com
5. Read this before using an AC terminator: http://www.sigcon.com/Pubs/news/2_24.htm
6. An excellent book on PCB layout: “Printed Circuit Board Design Techniques for EMC Compliance” by Mark Montrose.
Acknowledgements:
The author would like to thank engineers at Freescale for donating a Lite5200B development board for testing, and for reviewing this article for errors.
About the author:
Rick Miller has uncovered and solved signal integrity issues with a wide variety of customers worldwide. He holds a BS in EE from IIT, and a Masters from NU. He owns R Miller & Associates, Inc. and can be reached at www.RickMiller.com or 888-998-0100.
© 2006 R Miller & Associates, Inc. All rights reserved
Version 16, last update: 2006 June 26